Layout Design Engineer-临港(J11426)

Position Overview:　 Responsible for IC full-custom analog layout, verification of the layout (DRC/ERC/LVS), RC extraction for post simulation Responsibilities:　 Primary (70%): 1.Full custom analog layout/verification and RC extraction. 2.Perform block level layout. Conduct physical verification (DRC and LVS using Cadence tools). Secondary (30%): 1.Team work with analog designers, optimize layout. 2.Perform floor planning and placements (pad locations and custom routing). 【任职要求】 1..Experiences in Mixed signal/analog/high speed layout. 2.Familliar with layout skills and knowledge is must. 3.Good teamwork/communication/positive is must. 4.Familiar with Cadence IC layout and verification tools 5.Having massive IP block experience Plus: 1.Familiar with 0.18/0.13/0.09/0.065/0.04 um CMOS process and design rule is a plus. 2.Familiar with ESD/Latch up/antenna and related layout solutions is a plus. 3.Familiar with layout size reduction is a plus, with standard cell experience is good. 4.Familiar with rule deck is a plus.