Senior Software Design Engineer （NPU Compiler）(J11678)

1. Based on LLVM/MLIR, implement NPU compiler mid‑end and back‑end design, and perform quantization, loop tiling, pipelining, and other performance optimizations. 2. Build CNN/Transformer models using PyTorch/TensorFlow, complete the full workflow from training to inference. Evaluate end‑to‑end latency, throughput, and performance under different precisions (INT8/FP16). 3. Develop NPU kernel driver (interrupt, memory management), implement NPU+CPU co‑execution (task dependency, synchronization primitives, shared memory coherence), and provide runtime API for task scheduling. 4. Collaborate with the ASIC team on FPGA prototype and post‑silicon system verification, debug hardware/software interface issues, and perform execution testing and performance evaluation of the overall system. 【任职要求】 1. Deep understanding of IR, data flow analysis, loop transformations (tiling/fusion/unrolling), instruction selection, register allocation, and scheduling. 2. Familiarity with MLIR (dialect definition and lowering), TVM (schedule and TIR), or LLVM back‑end development. 3. Proficiency in parsing TFLite (FlatBuffer) and ONNX (Proto), handling quantization nodes; mastery of QAT/PTQ (INT8/INT4/FP16), per‑tensor/per‑channel quantization, and precision tuning. 4. Complete deployment experience on at least one NPU (e.g., Arm Ethos‑U, STM32N6), including driver, runtime API, memory management, and performance profiling. 5. Driver & co‑execution (mandatory): Experience in NPU kernel driver development and NPU+CPU heterogeneous execution (task dependency, synchronization primitives, shared memory coherence). FPGA/post‑silicon verification is a plus.