CIS WAT Layout Design Engineer(J11793)

CIS WAT layout design Engineer requires experience in the layout design and the analysis of wafer testing for CMOS device, working in close collaboration with CIS process integration engineers and pixel designers. • Comprehend device test structure requirement and perform hands-on layout design and verification • Analyze silicon testing results by using data analysis software and prepare a summary. • Organize device characteristics and wafer testing results to support CMOS image sensor development. • Collaborate with process integration, TCAD, and pixel design teams based on product requirements and schedules. 【任职要求】 •Bachelor's degree or higher in Semiconductor, Physics, Micro-Electronic, a related field, or equivalent work experience. •3+ years of experience in semiconductor PIE and devcie related experience. •1+ years of experience in test structure design using layout design tool. •Basic knowledge of semiconductors, MOS transistor structures, device performance. •Support daily operations and coordination for smooth project handling. •Understanding of CIS pixel structure and operation is a plus. •Result oriented and embraced change behaviors.