Serdes Analog top designer(J11321)

1. Analog top integration; 2. Analog schedule tracking and management; 3. Involved in analog ip spec definition; 4. Overall management on analog ip and serdes link test and debug; 5. Support CP/FT, reliability test, ESD, Latch-up, signal-integrity test, EMC test that everything leading to mass production; 【任职要求】 1. MSEE with 5+ years’ experience analog circuit design; 2. Hands-on experience in circuit design and debug; 3. good team work, self-driven and motivated; 4. good communication and presentation skills; 5. possessing below experience will be plus: 1) analog project leader and/or analog top integration; 2) serdes background; 3) familiar with chip scale knowledge, not just IP level; 4) LDO/Power-up block design; 5) good oral/written English skills;