Digital Verification Engineer – CIS(J11589)

1. Responsible for the verification of CIS image sensor, ISP image processing, and MIPI interface modules and subsystems. 2. According to CIS/ISP specifications, develop verification plans, extract test points, and complete functional verification, coverage-driven verification, boundary and exception scenario verification. 3. Build verification environments based on UVM methodology and develop verification components such as driver, monitor, scoreboard, sequence, and assertion. 4. Responsible for verification and protocol checking of key modules including image data path, RAW format, frame timing, clock synchronization, and MIPI CSI-2/D-PHY. 5. Perform simulation, debug RTL issues, analyze coverage, output verification reports, promote issue closure, and ensure tape-out quality. 6. Cooperate with design, system team to complete block-level and subsystem-level simulation verification. 7. Participate in the verification and checking of clock domain crossing, reset, low power, and timing-critical paths. 【任职要求】 1. Familiar with digital IC verification flow, proficient in UVM methodology, and able to build verification environments independently. 2. Proficient in Verilog/SystemVerilog hardware description language, and familiar with C/C++ language, with the ability to develop stimulus, design test cases, and compare results. 3. Familiar with mainstream EDA tools such as VCS/Xcelium and Verdi, proficient in coverage analysis, waveform debugging, and assertion-based verification. 4. Understand the CIS image sensor system architecture, ISP processing flow, and MIPI CSI-2/D-PHY interface protocols. 5. Understand typical image data formats, frame sync, line sync, and image data transmission mechanisms. 6. Experience in clock domain crossing, asynchronous timing, reset, and low-power verification is a plus. 7. Strong problem analysis and debugging skills, rigorous and responsible working attitude. Tape-out experience is a plus.