Digital Design Engineer(J14541)

- Write Micro-Architecture Definition/Writing Design Implementation Spec based on memory or storage feature requirements； - Write RTL coding for block or top level； - Do IP level synthesis / timing analysis / formality check / CDC check /Code coverage check； - Assist on Verification Engineer to complete module and top level simulation and verification; - Debug RTL/Gate Level waveform at module or top level; - Do Silicon debugging of the related module functionalities and provide ECO solution accordingly； 【任职要求】 - BS or MS in electric and electronic engineering； - Relevant experience in memory or storage design a plus; - Skills of Verilog RTL coding, simulation debug and base or metal layer ECO; - Hands on experience in EDA tools such as Cadence NC-Sim, Synopsys DC, PT, etc; - Skills of Script and be familiar with TCL, Perl, etc. - Self-motivated, good team work spirit and good communication skills; -有dram设计经验的优先